ChipCraftPlatform
Make the what-if cheap.
Bring your workload and constraints. Compare CPU and accelerator designs, test a proposed change, and keep a reproducible record of the decision. In a browser tab.
Transcript: Bring a workload. Make a decision. A real ChipCraftPlatform release-candidate workflow Start with your workload 8 × 8 signed integer matrix multiplication State the constraint 4,096 bytes of modeled on-chip capacity. Minimize latency. Compare CPU and accelerator within a budget 2 runs. The budget limits computation; it is not a performance estimate. Read the executed comparison CPU: 3,810 modeled cycles. Accelerator: 2,307. Both outputs verified. Find where the resources wait CPU, DMA and compute account for their own time. Overlapping waits are not added together. Review a proposed change A proposed change to the best verified configuration. It remains unmeasured until you run it. Check the measured consequence 300 fewer modeled cycles in this experiment. Export the review bundle The question, constraints, candidates and source identity travel together. Import. Rerun. Recover the decision. Fresh runs reproduce the outputs, modeled cycles and selected configuration. Modeled subsystem timing. Verified workload outputs. Task-level CPU and analytical memory. Capacity is not area. This profile has no energy estimate. Keep the decision. Keep the evidence. ChipCraftPlatform · chipcraftx.io/products/platform
Recorded on the release candidate: real executions, verified outputs and a fresh bundle rerun. Matrix and FIR subsystem studies use a task-level CPU, modeled memory timing and a fixed clock. This profile has no energy estimate.
Check the selected compute against RTL
Where RTL validation is available, replace the scalar accelerator compute with pinned RTL and compare the outputs and cycles on the same workload. The CPU, DMA, memory and fabric stay modeled.
An optional compute check, with retained evidence. This does not establish full-system RTL accuracy or silicon calibration.
Transcript: Check the selected compute boundary. An optional scalar RTL validation Keep the selected workload and configuration The fixed replacement supports one MAC per cycle. Model and RTL: outputs and cycles match 2,007 cycles each on this workload. The retained comparison keeps the artifact identity. RTL replaces scalar compute. The surrounding system stays modeled. CPU, DMA, memory and fabric remain transaction models. This is not full-system RTL or silicon calibration. Keep the decision. Keep the evidence. ChipCraftPlatform · chipcraftx.io/products/platform
These earlier recordings cover the existing CPU, accelerator and multicore workflows. Clock sweeps and uncalibrated energy estimates belong to those profiles; they are separate from the subsystem model above.
Transcript: Draw the system. Start from a template, or a blank canvas. The engine validates the architecture. Valid CXSim topology · no workload simulated. Change a parameter, save revision 2. Memory read latency 2 → 3 cycles. Revision 1 stays exactly as saved. Read latency is still 2 cycles there. Make the what-if cheap. Request access · chipcraftx.app/request-access
Draw the system
Start from a template, change a parameter, save a revision. The earlier one stays exactly as saved.
Transcript: One click, one comparison. One click: build, run, compare. The same ReLU job on the CPU core vs the accelerator. Same ReLU job: 6× faster with the accelerator. 2,897 simulated cycles on the CPU core, 480 on the accelerator. Modeled energy: 88.1% lower. Uncalibrated model: 8,356 pJ to 992 pJ. Make the what-if cheap. Request access · chipcraftx.app/request-access
One click, one comparison
The same ReLU job on the CPU core and on the accelerator: 2,897 vs 480 simulated cycles in this 32-element example.
Transcript: Where did the cycles go? A run's results come back verified. 2,897 simulated cycles, 32 kernel outputs checked. The CPU core waited 1,545 of 2,897 cycles. Waiting on memory or credit, not working. Then inspect the timeline, event by event. 1,855 recorded events across 28.97 µs. Make the what-if cheap. Request access · chipcraftx.app/request-access
Where did the cycles go?
Every run shows where its cycles went, down to single events.
Transcript: Nine designs, one submission. Sweep the clock: 9 configurations, one form. Objective: latency and modeled energy. Each configuration simulated in CXSim. Modeled trade-off: faster costs modeled energy. Frontier: 200 to 1,000 MHz. Below 200 MHz: slower and more energy. Least modeled energy at 200 MHz. 389.6 pJ at 2,400 ns, from an uncalibrated model. Make the what-if cheap. Request access · chipcraftx.app/request-access
Nine designs, one submission
Sweep the clock across nine configurations from one form and see the modeled trade-off.
Transcript: Where is parallel performance lost? One click: two cores, one shared memory bank. Each core sums its own array; CXSim runs both together. Where each processor's time went. Executing, memory service, queueing, waiting on a dependency, idle. core1 spends 12,837 of 32,680 cycles queueing for bank0. core0 queues 12,816 there too. Overlapping waits are never added up. The proposal: separate banks. Same 65,536 bytes in total, same 20-cycle latency, same workload. A hypothesis until it runs: about 19,843 cycles. An estimate, labeled as one. One click measures it. Measured: 1.647× faster, 39.3% sooner. 32,680 to 19,843 simulated cycles. Estimated 19,843, measured 19,843. One workload: here the estimate and the measurement agree. Both runs on one scale. Before: core0 and core1 share bank0, 32,680 cycles. After: the queueing is gone. Separate banks: 19,843 cycles. Keep the evidence: a shareable experiment. Held constant, what changed, evidence re-verified on every read. Transaction-level models. Not RTL. Not silicon. Cycles are simulated in CXSim; timing is modeled. Make the what-if cheap. Request access · chipcraftx.app/request-access
Where is parallel performance lost?
Two cores share one memory bank: see where each core's time goes, then measure what separate banks change.
Same workflow, two more cases: one where the estimate held, one where it did not.
Transcript: Who waits when a stream shares a bank? One click: a streaming writer and a compute core, one bank. core0 replays a scripted write stream, core1 runs a program. CXSim runs both together. Where each processor's time went. Executing, memory service, queueing, waiting on a dependency, idle. core1 spends 4,223 of 24,066 cycles queueing for bank0. The writer, core0, queues 1 cycle there. Overlapping waits are never added up. The proposal: separate banks. Same 65,536 bytes in total, same 20-cycle latency, same workload. A hypothesis until it runs: about 19,843 cycles. An estimate, labeled as one. One click measures it. Measured: 1.213× faster, 17.5% sooner. 24,066 to 19,843 simulated cycles. Estimated 19,843, measured 19,843. One workload: here the estimate and the measurement agree. Both runs on one scale. Before: core1 queues 4,223 cycles for bank0, 24,066 cycles in all. After: the queueing is gone. Separate banks: 19,843 cycles. Keep the evidence: a shareable experiment. Held constant, what changed, evidence re-verified on every read. Share it: copy the link. Anyone with access to this project can open this experiment. Transaction-level models. Not RTL. Not silicon. Cycles are simulated in CXSim; timing is modeled. Make the what-if cheap. Request access · chipcraftx.app/request-access
Streaming writer
A scripted write stream holds a bank while a compute core works. See who queues, then measure what separate banks change.
Transcript: Is the work evenly divided? One click: two cores, uneven work. core0 gets three ReLU tasks, core1 gets one. CXSim runs both together. Where each processor's time went. Executing, memory service, queueing, waiting on a dependency, idle. core1 is idle for 15,786 of 23,679 cycles. 66.7% of the run, while core0 is still working. The proposal: move r0 to core1. Same 65,536 bytes in total, same 20-cycle latency, same workload. Only r0's core changes. A hypothesis until it runs: about 15,786 cycles. An estimate, labeled as one. It assumes core1 and core0 do not queue. Measured: 1.403× faster, 28.7% sooner. 23,679 to 16,878 simulated cycles. Estimated 15,786, measured 16,878. 1,092 cycles above the estimate. The measurement replaces it. Both runs on one scale. Before: core1 is idle 15,786 cycles of 23,679. After: core1 is idle 21 cycles. core0 queues 1,092 cycles, equal to the gap above the estimate. core1 queues 1,071 cycles. Keep the evidence: a shareable experiment. Held constant, what changed, evidence re-verified on every read. Share it: copy the link. Anyone with access to this project can open this experiment. Transaction-level models. Not RTL. Not silicon. Cycles are simulated in CXSim; timing is modeled. Make the what-if cheap. Request access · chipcraftx.app/request-access
Uneven work
Three tasks on one core, one on the other. See the idle time, then measure moving one task.
Transcript: Share it, or take it with you. Share with a teammate as viewer or editor. They see it read-only. You can view saved revisions and results. Remove them, and access ends. Access for demo_teammate removed. Their link stops working. Project not found. Or take it with you: a reproducible bundle. Pinned architecture, workload, captured programs and model identity. Make the what-if cheap. Request access · chipcraftx.app/request-access
Share it, or take it with you
Share as a viewer or an editor, or export a reproducible bundle.