Idea → Prototype.
For all the stages of crafting a computer chip.
IDEA
→CREATE HW + SW
→SIMULATE
→GENERATE RTL
→PROTOTYPE
At the speed of thinking. In one platform.
For all computer architects.
PROVEN · PUBLIC BENCHMARKS
State of the Art.
Evaluated on public benchmarks across the hardware LLM research community. Scored against frontier models and published multi-agent systems. With full citations.
LIVE│LEADERBOARD::ACTIVE│67 ENTRIES│DB::ARXIV_SYNC
METRIC: PASS@1 / APR
Pinckney et al., NVIDIA · Si2 LLM Benchmarking Coalition · 2025 · Source ↗
FULL BENCHMARK · 5 CIDs · 302 PROBLEMSopen-source eval
USChipCraftX + Claude Opus 4.5286/302 · Iterative@5 · EDA validated
94.7%USChipCraftX + Claude Sonnet 4.6270/302 · Iterative@5 · EDA validated
89.4%USChipCraftX + Qwen3.6-35B261/302 · Iterative@5 · local FP8
86.4%Qwen3.6-35B (raw, thinking)187/302 · single-shot · no pipeline
61.9%Claude 3.7 SonnetPass@1 · 5-CID weighted avg[3]
43.6%GPT-4.1Pass@1 · 5-CID weighted avg[3]
39.0%Claude Haiku 4.5Pass@1[3]
31.8%LLaMA 3.1 405BOpen-source[3]
28.6%cid002 · CODE COMPLETION94 problems
Agentrys (ADA · Gen 6)APR · self-improving agent[11]
96.8%USChipCraftX + Claude Opus 4.588/94 · E 95.8% M 91.3%
93.6%USChipCraftX + Claude Sonnet 4.688/94 · E 95.8% M 91.3%
93.6%USChipCraftX + Qwen3.6-35B80/94 · local FP8 · APR
85.1%ACE-RTL (5×30 budget)APR · agentic system[4]
80.8%Qwen3.6-35B (raw, thinking)single-shot · no pipeline
47.9%GPT-5APR[4]
39.4%Claude 4 SonnetAPR[4]
39.4%DeepSeek-R1APR[4]
39.4%o4-miniAPR[4]
37.2%DeepSeek-v3.1APR[4]
37.2%Qwen3-Coder-480BAPR[4]
31.9%ScaleRTL†-32BRTL-specialized · APR[4]
29.8%Llama4-MaverickAPR[4]
28.7%cid003 · SPEC TO RTL78 problems
USChipCraftX + Claude Sonnet 4.676/78 · E 100% M 94.6%
97.4%USChipCraftX + Claude Opus 4.575/78 · E 100% M 91.9%
96.2%Agentrys (ADA · Gen 6)APR · self-improving agent[11]
96.2%ACE-RTL (5×30 budget)APR · agentic system[4]
96.2%USChipCraftX + Qwen3.6-35B74/78 · local FP8 · APR
94.9%Qwen3.6-35B (raw, thinking)single-shot · no pipeline
73.1%Claude 4 SonnetAPR[4]
51.3%ACE-RTL GeneratorPass@1[4]
49.7%DeepSeek-v3.1APR[4]
48.7%GPT-5APR[4]
47.4%o4-miniAPR[4]
45.5%DeepSeek-R1APR[4]
42.3%Qwen3-Coder-480BAPR[4]
35.9%cid004 · CODE MODIFICATION55 problems
USChipCraftX + Claude Opus 4.553/55 · E 96.7% M 96.0%
96.4%ACE-RTL (5×30 budget)APR · agentic system[4]
90.9%Agentrys (ADA · Gen 6)APR · self-improving agent[11]
90.9%USChipCraftX + Claude Sonnet 4.643/55 · E 80.0% M 76.0%
78.2%USChipCraftX + Qwen3.6-35B43/55 · local FP8 · APR
78.2%ACE-RTL GeneratorPass@1[4]
65.1%Qwen3.6-35B (raw, thinking)single-shot · no pipeline
56.4%Claude 4 SonnetAPR[4]
49.1%GPT-5APR[4]
45.5%o4-miniAPR[4]
44.4%DeepSeek-R1APR[4]
43.6%Qwen3-Coder-480BAPR[4]
41.8%Llama4-MaverickAPR[4]
38.2%cid007 · RTL OPTIMIZATION40 problems
USChipCraftX + Claude Opus 4.539/40 · E 95.5% M 100%
97.5%USChipCraftX + Claude Sonnet 4.632/40 · E 86.4% M 72.2%
80.0%USChipCraftX + Qwen3.6-35B31/40 · local FP8 · APR
77.5%Qwen3.6-35B (raw, thinking)single-shot · no pipeline
70.0%Claude 3.7 SonnetPass@1[3]
44.0%GPT-4.1Pass@1[3]
32.0%Claude Haiku 4.5Pass@1[3]
28.0%LLaMA 3.1 405BPass@1[3]
20.0%cid016 · BUG FIXING35 problems
Agentrys (ADA · Gen 6)APR · self-improving agent · Code Debug[11]
100.0%USChipCraftX + Qwen3.6-35B33/35 · local FP8 · APR
94.3%ACE-RTL (5×30 budget)APR · agentic system[4]
91.4%USChipCraftX + Claude Opus 4.531/35 · E 95.2% M 78.6%
88.6%USChipCraftX + Claude Sonnet 4.631/35 · E 90.5% M 85.7%
88.6%Qwen3.6-35B (raw, thinking)single-shot · no pipeline
74.3%GPT-5APR[4]
60.0%o4-miniAPR[4]
58.8%Claude 4 SonnetAPR[4]
54.3%DeepSeek-R1APR[4]
51.4%Qwen3-Coder-480BAPR[4]
42.9%REFERENCES
[1]MAGE: Multi-Agent Engine for RTL Code Generation · Source ↗
[2]VerilogEval: Liu et al., NVIDIA & UCSD, ICCAD 2023 · Source ↗
[3]CVDP: Pinckney et al., NVIDIA, 2025 · Source ↗
[4]ACE-RTL: Agentic RTL generation system, NVIDIA, Feb 2026 · Source ↗
[5]RealBench: Jin et al., Chinese Academy of Sciences, 2025 · Source ↗
[6]ChipBench: Zhong et al., UCSD & Columbia, ICML 2026 · Source ↗
[7]OpenLLM-RTL / RTLLM v2: Ahsan et al., HKUST, ICCAD 2024 · Source ↗
[8]Pluto: efficiency benchmark for LLM hardware code, ICLR 2026 · Source ↗
[9]ArchXBench: Purini et al., MLCAD 2025 · Source ↗
[10]ChipAgents: Alpha Design AI, Jan 2025 (press release) · Source ↗
[11]Agentrys: Agentic Design Automation (ADA), self-improving agent, Feb 2026 · Source ↗
All scores are pass@1 unless noted. ChipCraftX uses Iterative@5 with real EDA tool validation (compile → simulate → synthesize). Competitor scores sourced directly from cited papers. Additional benchmarks tracked: ResBench (Guo et al., HEART 2025, arXiv:2503.08823), RTLBench (IEEE ICCD 2025).
PIPELINE
The Right Agent
At Every Stage.
AGENT LEGEND
Kemal
HW Architect
Turns natural language into full SoC architecture specs.
Ayumi
RTL Engineer
Writes production-grade Verilog from architecture specs.
Mei
Verif Engineer
Reads your RTL, writes testbenches that match it.
Halo
Layout Engineer
Physical design oracle. Interprets P&R results and PPA.
Ravi
Bench Evaluator
Manages evaluation suites and feeds results back to the loop.
Dani
Training Engineer
Trains and fine-tunes the hardware LLMs.