ChipCraftVS Is Now on the Visual Studio Marketplace

ChipCraftVS brings the ChipCraftX agents into Visual Studio Code. Generate Verilog and SystemVerilog, review inline edits, and inspect simulation waveforms alongside your RTL. The extension is now available to install from the Visual Studio Marketplace.

ChipCraftModel-1: Our Own Model, at a Twentieth of the Price of Sonnet 5

ChipCraftModel-1 (CCM-1) is the first model in the ChipCraftModel family: a custom model trained on the ChipCraftX dataset and deployed on ChipCraftX infrastructure. It is not a general assistant that happens to know some Verilog. It is built for the whole RTL job - drafting a block to the interface it has to hit, refining it in steps, repairing what simulation rejects, and wiring the pieces into a system that boots. Because we train it and we host it, two things follow that a general-purpose API cannot offer: your unreleased design never reaches a third-party model provider, and the price is a fraction of frontier. CCM-1 runs at $0.10 per million input tokens and $0.50 per million output - a twentieth of Claude Sonnet 5, and a hundredth of a frontier model on blended cost. Early Access is open to design teams now.

“An unreleased architecture is the most sensitive thing a hardware team owns. CCM-1 exists so it never has to leave our infrastructure to get written, and so it costs a fraction of sending it somewhere else.”

ChipCraftBrain Paper Published on arXiv

Our research paper, ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration, is now published on arXiv. It formalizes the architecture behind our benchmark results: a hybrid symbolic-neural system that orchestrates six specialized agents over a 168-dimensional state space, combining pattern retrieval, hierarchical decomposition, and adaptive reinforcement learning to solve RTL generation at production accuracy.

Local Testbench Model: 100% semantic accuracy, zero API cost

We trained a dedicated testbench LLM that replaces all cloud API calls for testbench generation. When it produces a testbench that compiles, it passes simulation 100% of the time: zero semantic failures. Compilation-only failures account for the remaining 7.3% and are recoverable through iteration. This drops per-run testbench cost to zero and unblocks unlimited-budget preference training for the RTL model. The model was fine-tuned on a curated dataset of ~150K verified entries. Verify-before-train discipline is why the model achieves zero semantic failures on compiled outputs: it learned from exclusively correct signal and can expand to novel specs.

“Verification is the moat. Every piece we bring in-house makes the loop tighter.”

CVDP: 54.24% pass rate improvement over SOTA baseline while requiring only 1.28 iterations on average

The previous SOTA relied on fine-tuned models, massive compute budgets, and hundreds of retries. ChipCraftBrain solves the same problems in 1.28 iterations on average, lifting the pass rate by 54.24 percentage points through a fundamentally different approach.

“We invite all other competitors to publish their scores on CVDP and similar benchmarks for fair evaluation of the systems.”

VerilogEval 98.7%, #1 on the Benchmark

ChipCraftBrain achieves 98.72% pass rate on the full 156-problem VerilogEval functional benchmark, surpassing every published and commercial system, including MAGE (95.9%), ChipAgents (97.4%, closed-source), VFlow (83.6%), and CodeV (59.2%).