Build a single-clock 4-word, 8-bit FIFO.

- Synchronous reset clears occupancy, pointers, and registered read output.
- Preserve insertion order. A successful read updates dout at the clock edge.
- Block reads when empty; do not bypass a concurrent new write.
- Apply backpressure when full and no read is accepted.
- When full, accept a new write if a simultaneous read removes the oldest word.
- Expose wr_ready, rd_valid, full, empty, and used.

This brief, the original/revised RTL, and the testbench were authored for a
website demonstration. Simulation and synthesis results are captured by invoking
the current harness's EDA tool implementations locally. No model generation or
autonomous repair session is represented by this fixture.
